Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits

In this paper we propose a FPGA-based system to speed-up Fault Injection campaigns for the evaluation of the fault-tolerant capabilities of VLSI circuits. An environment is described, relying on FPGA-based emulation of the circuit. Suitable techniques are described, allowing emulating the effects of faults and to observe faulty behavior. The proposed approach allows combining the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures with respect to state-of-the-art simulation-based techniques can be achieved.